The invention relates, in general, to a method of manufacturing a flash memory device and, more particularly, to a method of forming a recess in an isolation layer.
In the case of a NAND flash memory device of 70 nm or less, greater interference between elements occurs in a multi-level cell (MLC) than in a single-level cell (SLC). Among the interferences affecting the elements, the interference between the floating gates is the greatest. In order to increase the reliability of a device, the interference between the floating gates should be reduced.
In a conventional manufacturing process for a flash memory device, the top surface of an isolation layer is recessed to reduce the interference between electrodes. However, it is difficult to improve yield and reliability because there are many process steps and thickness control is difficult.